1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a metal-oxide-semiconductor (MOS) transistor having a T-shaped gate electrode and a method for fabricating the same.
2. Description of the Related Art
With developments in the electronics industry, high integration and high-speed characteristics are becoming increasingly important in semiconductor devices. To meet such requirements, MOS transistors with various structures have been used for the semiconductor devices. Semiconductor devices with conventional MOS transistors, however, cannot completely satisfy the requirements of the high integration and high-speed characteristics.
FIG. 1 illustrates a cross-sectional view of a conventional MOS transistor. Referring to FIG. 1, a gate oxide layer 12 and a gate pattern 14 are sequentially stacked on a semiconductor substrate 10. A gate spacer 16 is disposed on both sidewalls of the gate pattern 14. A high-concentration impurity region 20 is disposed in the semiconductor substrate next to the gate spacer 16.
As the gate pattern 14 has become gradually finer with the increased integration of the semiconductor device, a distance between the high-concentration impurity regions 20, i.e., a distance between source and drain regions, has been gradually reduced. This reduced distance results in a short channel effect that causes severe degradation of characteristics of the semiconductor devices.
Generally, to minimize such a short channel effect, a low-concentration impurity region 18 is formed in the semiconductor substrate 10 under the gate spacer 16, as shown in FIG. 1. A structure having high- and low-concentration impurity regions 20 and 18 is typically called a “lightly doped drain (LDD) structure.”
However, even if the LDD structure minimizes the short channel effect caused by a shrinking of the width of the gate pattern 14, it is still difficult to shrink the width of the gate pattern 14 due to technical limitations. In addition, the fineness of the gate pattern 14 may cause problems other than the short channel effect, e.g., it may increase not only a resistance of a gate line, but also a capacitance between the gate pattern 14 and the high-concentration impurity region 20. Consequently, as the gate pattern 14 becomes gradually finer, it becomes more difficult to fabricate a high-speed semiconductor device.
FIG. 2 illustrates a cross-sectional view of a recently proposed, conventional MOS transistor with T-shaped gate electrode.
Referring to FIG. 2, a gate oxide layer 32 and a gate pattern 34 are sequentially stacked on a semiconductor substrate 30. The gate pattern 34 is a T-shaped structure including an undercut region. A gate spacer 36 is disposed on both sidewalls of the gate pattern 34 to fill the undercut region. A high-concentration impurity region 40 is disposed in the semiconductor substrate 30 next to the gate spacer 36. A low-concentration impurity region 38 is disposed in the semiconductor substrate 30 under the gate spacer 36 and the undercut region.
In the MOS transistor having the gate pattern 34 as shown in FIG. 2, a distance between the high-concentration impurity region 40 and the gate pattern 34 is wider by as much as about a width of the undercut region, as compared with the MOS transistor of FIG. 1. Accordingly, a capacitance between the gate pattern 34 and the high-concentration impurity region 40 may be reduced. In addition, a channel width of the semiconductor device may be reduced by as much as the width of the undercut region.
Unfortunately, however, a width of the low-concentration impurity region 38 is increased by as much as the width of the undercut region. This results in a problem such as an increase in a source/drain resistance Rsd of the transistor.